EP2A40F780 vs EP2A40B724C7 Vergleich
Detaillierter Direktvergleich von EP2A40F780 von Altera und EP2A40B724C7 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP2A40F780 - APEX II 1.5M Gate FPGA 780-pin FBGA | Intel
EP2A40F780 ⚠ Letzte Bestellmöglichkeit
Spezifikationsvergleich
| Parameter | EP2A40F780 | EP2A40B724C7 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $142,00 | $650,00 |
| Family | APEX II | APEX II |
| Device | EP2A40 | — |
| Typical Gates | 1,500,000 | — |
| Logic Elements | 30,000 | — |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O count] | — |
| Gehäuse | 780-ball FineLine BGA (FBGA) | 724-ball FCBGA (FineLine BGA), 35 mm x 35 mm |
| Montageart | Surface Mount | Surface Mount (BGA) |
| Betriebstemperatur | [DATA_NEEDED: temperature grade] | 0 °C to +85 °C (commercial) |
| Configuration Memory | SRAM-based | — |
| Embedded System Blocks (ESBs) | [DATA_NEEDED: ESB count] | — |
| Process Technology | [DATA_NEEDED: process node] | 0.15 µm CMOS, up to 8 metal layers, all-layer copper |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Programming File Format | .sof/.pof via Quartus II | — |
| Core Voltage | [DATA_NEEDED: VCCINT] | — |
| I/O Voltage | [DATA_NEEDED: VCCIO range] | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | Non-compliant (lead-bearing FCBGA) |
| Logic Elements / Cells | — | 38,400 |
| Total System Gates | — | 1,500,000 |
| Embedded RAM Bits | — | 655,360 |
| Maximum User I/O | — | 540 |
| Core Supply Voltage | — | 1.425 V to 1.575 V (typ. 1.5 V) |
| Maximum Internal Frequency | — | 562 MHz |
| PLLs | — | 4 |
| I/O Standards Supported | — | LVTTL, LVCMOS, 1.5 V/1.8 V/2.5 V/3.3 V, SSTL, HSTL, PCI, LVDS, LVPECL, PCML, HyperTransport, True-LVDS (1 Gbps) |
| Configuration Method | — | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel, Active Serial via EPC configuration devices |
| MultiVolt I/O Support | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V |
| DDR Memory Support | — | Yes (via ESB / I/O circuitry) |
| MSL-Level | — | [DATA_NEEDED: MSL level] |