EP2A70B724C7 vs EP2A70B724C7N Vergleich
Detaillierter Direktvergleich von EP2A70B724C7 von Intel und EP2A70B724C7N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP2A70B724C7 | EP2A70B724C7N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Unknown | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $188,00 |
| Device Type | FPGA (Field Programmable Gate Array) | FPGA (Field Programmable Gate Array) |
| Family | APEX II | APEX II (EP2A70) |
| Gate Count | 3,000,000 gates | — |
| Logic Cells | 67,200 cells | — |
| I/O Count | 540 I/O | — |
| Configuration or Memory Capacity | [DATA_NEEDED: exact embedded-memory or configuration-memory capacity] | — |
| Versorgungsspannung | 1.5 V | — |
| Maximum Frequency | 420 MHz | — |
| Fabrication Process | 0.15 µm | — |
| Loadable PLD Timing | 2.17 ns | — |
| Technology | CMOS | 0.15 µm CMOS |
| Gehäuse | 724-pin FCBGA, 724-BBGA, or PBGA724 | 724-pin FCBGA (Flip-Chip BGA) |
| Package Body Size | 35 mm x 35 mm | — |
| Package Pitch | 1.27 mm | — |
| Interface Capabilities | True-LVDS, LVPECL, PCML, and HyperTransport | — |
| RoHS-Status | unknown | [DATA_NEEDED: RoHS status] |
| REACH Status | unknown | — |
| AEC-Q100 Status | unknown | — |
| Lead-Free Status | unknown | — |
| Betriebstemperatur | [DATA_NEEDED: operating-temperature range] | 0 °C to +85 °C (Commercial) |
| System Gates | — | 3,000,000 |
| Logic Cells / Logic Elements | — | 67,200 |
| Maximum Internal Frequency | — | 420 MHz |
| Propagation Delay (typ.) | — | 2.17 ns |
| User I/O Pins | — | 536 |
| Macrocells (memory blocks reference) | — | 16 |
| Core Supply Voltage | — | 1.5 V nominal |
| I/O Supply Voltage | — | MultiVolt (1.5V / 1.8V / 2.5V / 3.3V / 5V tolerant) |
| Ball Pitch | — | 1.27 mm |
| Seated Height | — | 3.5 mm |
| Montageart | — | Surface Mount |
| Configuration Method | — | JTAG, Passive Serial (PS), Fast Passive Parallel (FPP) |
| PLL Count | — | [DATA_NEEDED: PLL count] |
| Embedded Memory | — | Embedded System Blocks (ESBs) - dual-port RAM / ROM / CAM |