EP2A70B724I8 vs EP2A70B724I-8 Vergleich
Detaillierter Direktvergleich von EP2A70B724I8 von Intel und EP2A70B724I-8 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP2A70B724I8 | EP2A70B724I-8 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $210,00 | $119,00 |
| Family | APEX II | APEX II |
| Logic Elements (LEs) | 67200 | — |
| System Gates | 3 M (typical maximum) | 3,000,000 |
| Process Technology | 0.15 µm CMOS | 0.15 µm CMOS |
| Core Voltage | 1.5 V | — |
| Maximum Internal Frequency | 281 MHz (typical) | 281 MHz |
| Gehäuse | 724-pin FCBGA | — |
| Pin-Anzahl | 724 | — |
| Operating Temperature (Industrial) | -40 °C to +100 °C | — |
| Speed Grade | 8 | — |
| Embedded Memory | ESB / TriMatrix (size not in provided data) | — |
| Configuration Modes | Active Serial, Passive Serial, Passive Parallel Asynchronous | — |
| PLL Count | [DATA_NEEDED: PLL block count] | — |
| User I/O Banks | [DATA_NEEDED: bank count and I/O count] | [DATA_NEEDED: user I/O bank count] |
| Multipliers | Embedded multiplier blocks (count [DATA_NEEDED]) | — |
| Supported I/O Standards | LVTTL, LVCMOS, SSTL, LVDS (True-LVDS), PCI, HSTL | — |
| Montageart | Surface Mount (BGA) | Surface Mount |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Configuration Device Compatibility | EPC4, EPC8, EPC16 (Enhanced Configuration Devices) | — |
| Design Software | Quartus II (legacy support) | — |
| Logic Elements / Cells | — | 67,200 cells |
| Core Supply Voltage | — | 1.5 V |
| I/O Supply Voltage | — | 3.3 V |
| Anzahl der Pins | — | 724 |
| Package Type | — | FCBGA (Flip-Chip Ball Grid Array) |
| Betriebstemperatur | — | -40 °C to +100 °C (Industrial) |
| Peak Reflow Temperature | — | 220 °C (per JEDEC J-STD-020) |
| User I/O Pins | — | [DATA_NEEDED: user I/O pin count] |
| Embedded System Blocks (ESBs) | — | [DATA_NEEDED: ESB count] |
| Embedded Array Blocks (EABs) | — | [DATA_NEEDED: EAB count] |
| Embedded RAM | — | [DATA_NEEDED: total bits] |
| PLLs | — | [DATA_NEEDED: PLL count] |
| Configuration Method | — | JTAG / Passive Serial / Passive Parallel |
| MSL-Level | — | [DATA_NEEDED: MSL level] |