EP2A70F1508I-7 vs EP2A70F1508C8 Vergleich
Detaillierter Direktvergleich von EP2A70F1508I-7 von Intel und EP2A70F1508C8 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP2A70F1508I-7 | EP2A70F1508C8 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $140,00 | $1.495,00 |
| Family | APEX II | — |
| Series | EP2A | APEX II (EP2A70) |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements (LE) | 70,000 | — |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Gehäuse | 1508-ball FineLine BGA | 1508-BBGA, FCBGA (40 x 40 mm) |
| Montageart | Surface Mount | Surface Mount (BGA) |
| Operating Temperature Grade | Industrial (I suffix) | — |
| Speed Grade | -7 | — |
| Peak Reflow Temperature | 220 C | — |
| Feuchtigkeitsempfindlichkeitsgrad (MSL) | 3 | — |
| Configuration Interface | Serial ROM / Parallel ROM / JTAG | — |
| Embedded Memory | Embedded System Blocks (ESB) for RAM/ROM/FIFO | — |
| Multipliers | Dedicated hardware multiplier blocks | — |
| I/O Standards | LVTTL, LVCMOS, LVDS, PCI, GTL+, SSTL | — |
| Design Tool | Quartus II | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Versorgungsspannung | [DATA_NEEDED: VCCINT/VCCIO] | — |
| Device Family | — | APEX II |
| Logic Elements | — | 67,200 |
| Embedded RAM Bits | — | 1,146,880 |
| User I/O Count | — | 1060 |
| Maximum User I/O Pins | — | 1060 |
| Process Technology | — | 0.15 µm all-layer copper, up to 8 metal layers |
| Core Voltage | — | 1.425 V to 1.575 V (1.5 V nominal) |
| Betriebstemperatur | — | 0 °C to 85 °C (commercial) |
| High-Speed Interface Support | — | 1 Gbps True-LVDS, LVPECL, PCML, HyperTransport |
| Speichertyp | — | Embedded dual-port RAM / ROM via ESBs |
| Architecture | — | Embedded array with LABs + ESBs |