EP2AGX65CU17C5N vs EP2AGX65CU17I5G Vergleich
Detaillierter Direktvergleich von EP2AGX65CU17C5N von Intel und EP2AGX65CU17I5G von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP2AGX65CU17C5N | EP2AGX65CU17I5G |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Unknown |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $178,40 | $0,00 |
| Family | Arria II GX | — |
| Logic Elements | 60,214 | 60,214 |
| LABs/CLBs | 2,530 | — |
| Total Memory Bits | 5,371,904 bits (4.4 Mb) | — |
| Maximum User I/O | 156 | — |
| User I/O Banks | 9 (typical, package-dependent) | — |
| Gehäuse | 358-ball FC-UFBGA (UBGA) | 358-ball LFBGA, FCBGA |
| Process Technology | 40 nm TSMC low-power | — |
| Core Voltage | 0.9 V | [DATA_NEEDED: core voltage] |
| Transceivers | Up to 16 multi-gigabit transceivers | — |
| Max Transceiver Data Rate | 6.375 Gbps | — |
| PLLs | 8 | — |
| DSP Blocks | 6 × 6 hardened multipliers | — |
| Speed Grade | C5 (middle-speed) | — |
| Temperature Grade | N (extended, -40 °C to +100 °C Tj) | — |
| Hard PCIe Gen1/Gen2 | Yes (with PIPE interface) | — |
| Configuration Modes | FPP, PS, JTAG, EPCS | — |
| Montageart | Surface Mount (BGA) | Surface Mount |
| Device Type | — | Field Programmable Gate Array (FPGA) |
| Product Family | — | Arria II GX |
| Programmable Logic Bits | — | 5,371,904 |
| User I/O Count | — | 156 |
| Number of Terminals | — | 358 |
| Terminal Form | — | Ball |
| Package Code | — | LFBGA |
| Package Shape | — | Square |
| Logic Cell Count | — | 60,214 |
| I/O Count | — | 156 |
| RoHS-Status | — | Compliant |
| Lead Free Status | — | Not stated in verified data |
| Betriebstemperaturbereich | — | [DATA_NEEDED: operating temperature range] |
| I/O Voltage Support | — | [DATA_NEEDED: I/O voltage support] |
| Transceiver Count | — | [DATA_NEEDED: transceiver count] |
| Maximum Transceiver Data Rate | — | [DATA_NEEDED: maximum transceiver data rate] |
| Configuration Memory | — | [DATA_NEEDED: configuration memory] |
| Package Dimensions | — | [DATA_NEEDED: package dimensions] |
| Embedded Memory | — | [DATA_NEEDED: embedded memory] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |