EP2AGZ350FF35C4G vs EP2AGZ350FF35I3 Vergleich
Detaillierter Direktvergleich von EP2AGZ350FF35C4G von Intel und EP2AGZ350FF35I3 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP2AGZ350FF35C4G | EP2AGZ350FF35I3 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $1.395,00 | $4.409,18 |
| Series | Arria II GZ | Arria II GZ |
| Family | Arria II GZ | — |
| Logic Elements (LEs) | Approx. 350,000 [DATA_NEEDED: exact LE count from datasheet] | — |
| Process Node | 40 nm | 40 nm |
| Gehäuse | 1152-ball FC-FBGA (FF35) | 1152-ball FCBGA (FF35) |
| User I/Os | 554 | — |
| Speed Grade | C4 (slowest) | — |
| RoHS-Status | Compliant (G suffix) | Compliant per distributor listings |
| Montageart | Surface Mount (BGA) | — |
| Supply Voltage (Core) | [DATA_NEEDED: Vcore value from datasheet] | 0.9 V typical [DATA_NEEDED: full range from datasheet] |
| Supply Voltage (I/O) | [DATA_NEEDED: Vio value from datasheet] | — |
| Embedded Transceivers | Yes, multi-gigabit (data rate [DATA_NEEDED]) | — |
| DSP Blocks | Yes (count [DATA_NEEDED]) | — |
| Embedded Memory | M9K + M144K blocks (total bits [DATA_NEEDED]) | — |
| Betriebstemperatur | Commercial (0C to +85C) [DATA_NEEDED: exact range] | — |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements (LE) | — | 348,500 |
| Embedded Memory Bits | — | 21,270,528 bits |
| Embedded Memory (M9K/M144K) | — | [DATA_NEEDED: block count and distribution] |
| Maximum User I/O | — | 554 |
| Transceivers | — | Up to 16 channels |
| Transceiver Data Rate | — | 6.375 Gbps |
| DSP Blocks (18x19 multipliers) | — | [DATA_NEEDED: exact multiplier count, datasheet lists up to ~1,368] |
| Ball Pitch | — | 1.0 mm |
| Operating Temperature Grade | — | Industrial (-40C to +100C Tj) |
| Configuration Method | — | FPGA configuration via Altera Quartus II |
| Hard IP Blocks | — | PCIe Gen2 hard IP, memory controllers, PLLs |
| MSL-Level | — | 3 (per typical Altera FCBGA handling) |