EP2C8T144I8N vs EP2C8T144C6 Vergleich
Detaillierter Direktvergleich von EP2C8T144I8N von Intel und EP2C8T144C6 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP2C8T144I8N - Cyclone II FPGA, 8K LEs, 144-TQFP | Intel
EP2C8T144I8N ⚠ Letzte Bestellmöglichkeit
Spezifikationsvergleich
| Parameter | EP2C8T144I8N | EP2C8T144C6 |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $17,50 | $22,62 |
| Family | Cyclone II | Cyclone II |
| Logic Elements (LEs) | 8,256 | — |
| Total Memory Bits | 165,888 | — |
| Embedded Memory Blocks | 36 (M4K) | — |
| Embedded Multipliers (18x18) | 36 | — |
| Maximum User I/O Pins | 85 | — |
| Gehäuse | 144-pin TQFP (TQFP-144) | 144-pin LQFP (TQFP), 22x22 mm, 0.5 mm pitch |
| Process Technology | 90 nm TSMC low-k dielectric | 90 nm CMOS |
| Core Voltage (VCCINT) | 1.2 V | — |
| I/O Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| PLLs | 2 | 4 |
| Configuration Modes | AS, PS, JTAG | — |
| Maximum Operating Frequency | 402.58 MHz | — |
| Betriebstemperaturbereich | -40C to +100C (Industrial) | Commercial (0C to +85C) |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | Compliant | Non-compliant (per distributor listing) |
| Speed Grade | -8 | 6 |
| Logic Elements (LE) | — | 8,256 |
| Configurable Logic Blocks (CLB) | — | 516 |
| Embedded Memory (bits) | — | 165,888 |
| Embedded RAM Blocks | — | 36 M4K blocks (4,608 bits each) |
| Embedded 18x18 Multipliers | — | 18 |
| User I/O Pins (max) | — | 85 |
| Maximum User I/O (this package) | — | 85 |
| Core Voltage | — | 1.2 V (typical) |
| Configuration Interface | — | JTAG (IEEE 1149.1), Altera AS / PS / PP |
| Design Software | — | Quartus II (v13.0 SP1 recommended) |
| Maximum Internal Frequency | — | [DATA_NEEDED: see Cyclone II device handbook for fMAX by design] |