EP2S15F672C5N vs EP2S15F672C4 Vergleich
Detaillierter Direktvergleich von EP2S15F672C5N von Intel und EP2S15F672C4 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP2S15F672C5N | EP2S15F672C4 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $121,90 | $235,00 |
| Family | Stratix II | Stratix II |
| Series | Altera Stratix II | — |
| Logic Elements | 15,600 | 15,600 |
| Logic Array Blocks (LABs) | 780 | — |
| Configurable Logic Blocks (CLBs) | 6,240 | — |
| Embedded Memory (bits) | 419,328 | — |
| User I/O Pins | 366 | — |
| Gehäuse | 672-BBGA / FBGA-672 | 672-ball FineLine BGA (FBGA) |
| Package Dimensions | 35 x 35 mm | — |
| Ball Pitch | 1.0 mm | — |
| Maximum Internal Frequency | 640 MHz | — |
| Betriebstemperatur | 0C to +85C (commercial) | Commercial (0C to +85C, 'C' suffix) |
| Speed Grade | -C5 | 4 |
| Lead-Free (Pb-Free) | Yes | — |
| RoHS-Status | RoHS Compliant | [DATA_NEEDED: RoHS compliance per Altera product page] |
| Embedded Memory Bits | — | 419,328 bits |
| DSP Blocks | — | 156 (approximate, per Stratix II family) |
| Maximum User I/Os | — | 366 |
| Process Node | — | 90 nm |
| PLLs | — | 6 |
| Configuration Method | — | Serial / Parallel (passive serial, fast passive parallel, JTAG) |
| I/O Standards Supported | — | LVTTL, LVCMOS, LVDS, SSTL, HSTL (per Stratix II family) |
| Lead-Free | — | [DATA_NEEDED: lead-free finish status] |
| MSL-Level | — | [DATA_NEEDED: MSL moisture sensitivity level] |