EP2S30F484I4N vs EP2S30F484C5 Vergleich
Detaillierter Direktvergleich von EP2S30F484I4N von Intel und EP2S30F484C5 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP2S30F484C5 - Stratix II FPGA 33,880 Logic Elements | Altera/Intel
EP2S30F484C5 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP2S30F484I4N | EP2S30F484C5 |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $305,00 | $305,40 |
| Family | Stratix II | Stratix II |
| Logic Elements | 33,880 | 33,880 |
| Embedded Memory | 1,369,728 bits | — |
| User I/O Pins | 342 | — |
| Gehäuse | 484-ball FineLine BGA (FBGA) | — |
| Ball Pitch | 1.0 mm | — |
| Process Technology | 90 nm | 90 nm CMOS |
| Core Voltage | 1.2 V (refer to datasheet) | — |
| Operating Temperature Grade | Industrial -40C to +100C | — |
| Lead-Free / RoHS | Yes (N suffix indicates lead-free RoHS) | — |
| Speed Grade | 4 | C5 (commercial) |
| On-Chip DSP Blocks | Yes (dedicated 9x9/18x18/36x36 multipliers) | — |
| PLLs | Yes (on-chip, refer to datasheet for count) | — |
| Configuration Method | Serial/parallel via Quartus II | — |
| Montageart | Surface Mount (BGA) | Surface Mount |
| Number of LABs/CLBs | — | 1,694 |
| Total RAM Bits | — | 1,369,728 |
| Number of I/Os | — | 342 |
| Number of Gates | — | [DATA_NEEDED: gate count equivalence for EP2S30] |
| Voltage - Supply | — | 1.2 V core |
| Betriebstemperatur | — | 0C to +85C (commercial, C5 grade) |
| Gehäuse / Bauform | — | 484-BBGA, FC-FBGA |
| Package Dimensions | — | [DATA_NEEDED: 484-FBGA body size] |
| Supplier Device Package | — | 484-FBGA |
| RoHS-Status | — | [DATA_NEEDED: lead-free/RoHS confirmation for EP2S30F484C5] |
| MSL-Level | — | [DATA_NEEDED: MSL rating for FBGA484] |
| DSP Blocks | — | 16 embedded multiplier blocks (family-level) |
| Maximum Frequency | — | 609.76 MHz (family reference) |