EP2S60F1020 vs EP2S60F1020I4 Vergleich
Detaillierter Direktvergleich von EP2S60F1020 von Altera und EP2S60F1020I4 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP2S60F1020 - Stratix II FPGA, 60K LEs, 1020-BBGA | Altera
EP2S60F1020 ⚠ Letzte Bestellmöglichkeit
Spezifikationsvergleich
| Parameter | EP2S60F1020 | EP2S60F1020I4 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $1.495,00 | $1.454,92 |
| Family | Stratix II | — |
| Logic Elements (LE) | 60,440 | — |
| Adaptive Logic Modules (ALM) | 30,220 | — |
| Total Embedded Memory Bits | 2,544,192 bits | — |
| Embedded Memory Type | TriMatrix (M512 / M4K / M-RAM) | — |
| DSP Blocks | 36 (18x18 multipliers) | — |
| Maximum User I/O | 718 | 718 |
| Gehäuse | 1020-BBGA (flip-chip BGA) | — |
| Process Technology | 90 nm | 90 nm CMOS |
| Supply Voltage (Core) | 1.2 V | — |
| Configuration Modes | Passive Serial, Fast Passive Parallel, JTAG | — |
| PLLs | 12 (4 enhanced + 8 fast) | — |
| Bitstream Encryption | 128-bit AES | — |
| Operating Temperature Grades | Commercial (C), Industrial (I) | — |
| RoHS-Status | Compliant (lead-free variants available) | Non-compliant (contains lead per legacy Altera package) |
| Manufacturer | — | Intel / Altera |
| Series | — | Stratix II |
| Logic Elements (LEs) | — | 60,440 |
| Embedded Memory (bits) | — | 2,544,192 |
| Number of LABs/CLBs | — | 3022 |
| Number of CLBs | — | 24176 |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Operating Voltage (Core) | — | 1.2 V |
| Temperature Grade | — | Industrial (-40C to +100C TJ) |
| Package Type | — | 1020-ball FC-FBGA (Fine-pitch Chip-Scale BGA) |
| Package Dimensions | — | 33 mm x 33 mm |
| Ball Pitch | — | 1.0 mm |
| Montageart | — | Surface Mount |
| Configuration Method | — | Passive Serial / Fast Passive Parallel / JTAG |
| Number of PLLs | — | 12 |
| Global Clock Networks | — | 16 |
| Embedded Multipliers (18x18) | — | 36 |
| Transceiver Count | — | 0 (no embedded transceivers) |
| Maximum Embedded Memory Bandwidth | — | [DATA_NEEDED: memory bandwidth spec] |