EP2S60F484C3 vs EP2S60F484I4 Vergleich

Detaillierter Direktvergleich von EP2S60F484C3 von Altera und EP2S60F484I4 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP2S60F484C3 EP2S60F484I4
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $92,00 $138,40
Series Stratix II Stratix II
Manufacturer Altera (now Intel FPGA) Intel (formerly Altera)
Logic Elements 60,440 —
Adaptive Logic Modules (ALMs) 24,176 —
LABs/CLBs 3,022 —
Total RAM Bits 2,544,192 —
User I/O Count 334 —
Gehäuse 484-BBGA, FCBGA (FBGA-484) 484-ball FBGA (F484)
Package Size 23 x 23 mm, 1.0 mm pitch —
Core Voltage 1.2 V 1.2 V
Process Technology 90 nm CMOS 90 nm CMOS
Speed Grade C3 I4 (industrial, fastest speed bin for Stratix II F484)
Betriebstemperatur 0C to +85C (commercial) —
Number of PLLs 12 (Stratix II typical) —
Montageart Surface Mount Surface Mount
RoHS-Status [DATA_NEEDED: RoHS status] —
Total Multipliers 12 (9-bit embedded multiplier blocks) —
Family — Stratix II FPGA
Logic Elements (LE) — 60,440
Adaptive Logic Modules (ALM) — [DATA_NEEDED: ALM count]
Embedded Memory Bits — 2,544,192 bits (~317 KB)
Total RAM Blocks — [DATA_NEEDED: total RAM blocks]
User I/O Pins — 334
User I/O Banks — [DATA_NEEDED: I/O bank count]
High-Speed Transceivers — 12 channels
Transceiver Data Rate — [DATA_NEEDED: max Gbps]
PLLs — 4
DSP Blocks — [DATA_NEEDED: DSP block count]
Betriebstemperaturbereich — -40 °C to +100 °C (Industrial, I4)
Ball Pitch — [DATA_NEEDED: ball pitch in mm]
Lead-Free / RoHS — Contains Lead; RoHS Non-Compliant (per distributor data)
Configuration Method — SRAM-based, loaded via Quartus II bitstream
MSL-Level — [DATA_NEEDED: MSL rating]

Datenblätter & Ressourcen

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