EP2S60F484C3N vs EP2S60F484I4 Vergleich

Detaillierter Direktvergleich von EP2S60F484C3N von Intel und EP2S60F484I4 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP2S60F484C3N EP2S60F484I4
Marke Intel Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $1.245,75 $138,40
Family Stratix II Stratix II FPGA
Logic Elements 60,440 —
Adaptive LUTs (ALUTs) 48,352 —
Embedded Memory (TriMatrix) 2,544 Kbits (M4K + M512 + M-RAM) —
Embedded DSP Blocks 12 (48 GMACs at 450 MHz) —
Maximum User I/O Pins 334 —
Gehäuse 484-BGA (F484), 1.0 mm pitch 484-ball FBGA (F484)
Process Technology 90 nm CMOS, 1.2 V core 90 nm CMOS
Speed Grade -3 (fastest commercial) I4 (industrial, fastest speed bin for Stratix II F484)
Operating Temperature (Commercial) 0C to +85C (TJ) —
Supply Voltage VCCINT 1.2 V nominal —
Configuration Modes FPP, AS, PS, JTAG —
MSL-Level 3 (per JEDEC J-STD-020) [DATA_NEEDED: MSL rating]
RoHS-Status Compliant —
Lead-Free Yes —
Series — Stratix II
Manufacturer — Intel (formerly Altera)
Logic Elements (LE) — 60,440
Adaptive Logic Modules (ALM) — [DATA_NEEDED: ALM count]
Embedded Memory Bits — 2,544,192 bits (~317 KB)
Total RAM Blocks — [DATA_NEEDED: total RAM blocks]
User I/O Pins — 334
User I/O Banks — [DATA_NEEDED: I/O bank count]
High-Speed Transceivers — 12 channels
Transceiver Data Rate — [DATA_NEEDED: max Gbps]
PLLs — 4
DSP Blocks — [DATA_NEEDED: DSP block count]
Core Voltage — 1.2 V
Betriebstemperaturbereich — -40 °C to +100 °C (Industrial, I4)
Ball Pitch — [DATA_NEEDED: ball pitch in mm]
Montageart — Surface Mount
Lead-Free / RoHS — Contains Lead; RoHS Non-Compliant (per distributor data)
Configuration Method — SRAM-based, loaded via Quartus II bitstream

Datenblätter & Ressourcen

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