EP2S60F484I5N vs EP2S60F484C5N Vergleich

Detaillierter Direktvergleich von EP2S60F484I5N von Altera und EP2S60F484C5N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Intel
EP2S60F484C5N EP2S60F484C5N - 60K LE Stratix II FPGA, 484-FBGA | Intel

EP2S60F484C5N - 60K LE Stratix II FPGA, 484-FBGA | Intel

EP2S60F484C5N ⚠ Letzte Bestellmöglichkeit

Spezifikationsvergleich

Parameter EP2S60F484I5N EP2S60F484C5N
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Letzte Kaufgelegenheit
Lagerstatus In Stock In Stock
Stückpreis (USD) $1.325,00 $720,50
Series Stratix II (EP2S60) —
Family Field Programmable Gate Array (FPGA) Stratix II
Logic Elements (LE) 60,440 —
Adaptive Logic Modules (ALM) 24,176 —
Embedded Memory (bits) 2,544,192 —
Embedded Memory (M512/M4K/M-RAM blocks) M512: 330, M4K: 255, M-RAM: 2 —
DSP Blocks (18-bit multipliers) 48 blocks (192 18x18 multipliers) —
PLLs 12 (4 enhanced + 8 fast) 12 (enhanced + fast)
Maximum User I/O Pins 334 —
Maximum Fabric Clock 609.76 MHz —
Core Supply Voltage 1.2 V typical —
Process Technology 90 nm CMOS 90 nm CMOS
Gehäuse 484-ball FC-FBGA (Flip-Chip Fine-pitch BGA), 1.00 mm pitch 484-ball FBGA (FineLine BGA)
Speed Grade I5 (industrial, slow-speed for low power) C5 (slowest)
Betriebstemperaturbereich -40 °C to +100 °C (industrial) —
Montageart Surface Mount (BGA) —
RoHS-Status [DATA_NEEDED: rohs status not stated in verified data] Compliant (lead-free)
Lead-Free / Halogen-Free [DATA_NEEDED: lead-free / halogen-free status] —
Configuration Interface JTAG (IEEE 1149.1), Passive Serial, Fast Passive Parallel —
Design Tool Quartus II (legacy; current Intel Quartus Prime with Stratix II device support) —
Logic Elements — 60,440
Adaptive Logic Modules (ALMs) — 24,176
Embedded Memory Bits — 2,544,192 bits
Embedded RAM Blocks (TriMatrix) — Yes
DSP Blocks — 36
18x18 Multipliers — Up to 144 (max for family: 384)
Maximum User I/O — 334
Transceiver Blocks — 12 (up to 6.375 Gbps)
Core Voltage — 1.2 V
I/O Standards — LVTTL, LVCMOS, LVDS, LVPECL, PCI, PCI-X
Temperature Grade — Commercial (0C to +85C junction)
Configuration Scheme — SRAM-based, volatile (requires EPC16/EPC64 or JTAG)

Datenblätter & Ressourcen

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