EP2S60F672C5 vs EP2S60F672C4 Vergleich
Detaillierter Direktvergleich von EP2S60F672C5 von Intel und EP2S60F672C4 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP2S60F672C5 | EP2S60F672C4 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $410,85 | $1.080,00 |
| Family | Stratix II | Stratix II |
| Device Family | Stratix II FPGA | — |
| Logic Elements | 60,440 | — |
| Configurable Logic Blocks (CLBs) | 24,176 | — |
| Total RAM Bits | 2,544,192 bits | — |
| Maximum User I/Os | 492 | — |
| Operating Frequency | Up to 609.76 MHz | — |
| Core Voltage | 1.2 V | 1.2 V (typical) |
| Process Technology | 90 nm CMOS | 90 nm |
| Gehäuse | 672-ball FC-FBGA (35 × 35 mm, 1 mm pitch) | 672-BBGA, FCBGA |
| Montageart | Surface Mount | Surface Mount |
| Operating Temperature Grade | Commercial (C5 suffix) | — |
| Betriebstemperaturbereich | 0°C to +85°C | — |
| Number of PLLs | 4 | — |
| DSP Blocks | 12 (dedicated 18 × 18 multipliers) | [DATA_NEEDED: DSP block count per Stratix II variant] |
| I/O Standards | LVDS, LVTTL, SSTL, HSTL, PCI-X | — |
| Configuration Scheme | Fast Passive Parallel, JTAG, Active Serial | — |
| RoHS-Status | Non-RoHS (legacy product, pre-RoHS production runs) | [DATA_NEEDED: not confirmed in provided data] |
| Logic Elements (LE) | — | 60440 |
| Embedded Memory Bits | — | 2544192 |
| Logic Array Blocks (LAB) | — | 3022 |
| User I/Os | — | 492 |
| Betriebstemperatur | — | 0C to +85C (commercial) |
| Speed Grade | — | C4 |
| Lead-Free | — | [DATA_NEEDED: not confirmed in provided data] |
| MSL-Level | — | [DATA_NEEDED: not in provided data] |