EP2SGX60E1152C vs EP2SGX60EF1152I4N Vergleich
Detaillierter Direktvergleich von EP2SGX60E1152C von Intel und EP2SGX60EF1152I4N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP2SGX60E1152C | EP2SGX60EF1152I4N |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $1.218,00 | $0,00 |
| Family | Stratix II GX | — |
| Logic Elements | 60440 | — |
| On-chip RAM (bits) | 2544192 | — |
| DSP / Embedded Multiplier Blocks | 144 (18x18 multipliers) | — |
| Maximum User I/O | 534 | — |
| Gehäuse | 1152-ball FineLine BGA | 1,152-ball FBGA |
| Betriebstemperatur | 0C to +85C (commercial) | — |
| Speed Grade | C (commercial, fastest) | — |
| Process Node | 90 nm | — |
| Multi-gigabit Transceivers | 20 channels | — |
| Transceiver Data Rate | 600 Mbps to 6.375 Gbps | — |
| PCI Express Hard IP | x1, x4, x8 endpoints and root ports | — |
| Embedded Memory Type | TriMatrix (MLAB + M512 + M4K) | — |
| Configuration | Active serial / Fast passive parallel / JTAG | — |
| RoHS-Status | Compliant | — |
| Device Type | — | FPGA |
| Product Family | — | Stratix II GX |
| Logic Cells | — | 60,440 |
| Embedded Memory | — | 2,544,192 bits |
| I/O Count | — | 534 |
| Internal Frequency | — | 717 MHz |
| Versorgungsspannung | — | 1.2 V |
| Package Type | — | Other, 23 x 23 mm, 1 mm pitch, MS-034AAJ-1, FBGA-484 |
| Pins | — | 484 |
| Device Technology | — | 90 nm |
| Logic Blocks | — | 3,022 LABs |
| Montageart | — | Surface mount |
| Operating Temperature Grade | — | Industrial |
| Compliance | — | [DATA_NEEDED: compliance certification details] |
| Transceiver Count | — | [DATA_NEEDED: high-speed transceiver count] |
| Configuration Memory | — | [DATA_NEEDED: configuration memory specification] |
| Package Pinout | — | [DATA_NEEDED: complete ball-map pinout] |