EP2SGX90FF1508 vs EP2SGX90FF1508C5N Vergleich
Detaillierter Direktvergleich von EP2SGX90FF1508 von Altera und EP2SGX90FF1508C5N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP2SGX90FF1508 | EP2SGX90FF1508C5N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $1.380,00 |
| Product Type | Field Programmable Gate Array (FPGA) | — |
| Device Family | Stratix II GX | — |
| Logic Cell Count | 90,960 cells | — |
| Logic Element Count | 90,960 elements | — |
| User I/O Count | 650 I/O | — |
| RAM Bits | 4,520,448 bits | — |
| LAB Count | 4,548 LABs | — |
| Versorgungsspannung | 1.2 V | — |
| Listed Frequency | 816.9 MHz | — |
| Related Speed-Grade Frequency | 717 MHz | — |
| Technology | CMOS | — |
| Package Type | FCBGA | — |
| Package Pin Count | 1,508 balls | — |
| Package Body Size | 40 mm x 40 mm | — |
| Ball Pitch | 1 mm | — |
| Package Outline Reference | MS-034AAU-1 | — |
| Montageart | Surface mount | Surface Mount (BGA) |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | Commercial (0C to +85C junction) |
| RoHS-Status | [DATA_NEEDED: RoHS status] | — |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Lead-Free Status | Lead-free | — |
| Family | — | Stratix II GX |
| Logic Elements (LEs) | — | 90,960 |
| Logic Array Blocks (LABs) | — | 4,548 |
| Total RAM Bits | — | 4,520,448 |
| User I/O Pins | — | 650 |
| Gehäuse | — | 1508-ball FCBGA (FBGA-1508), 40 x 40 mm, 1 mm pitch |
| Process Node | — | 90 nm CMOS |
| Core Voltage (VCCINT) | — | 1.2 V |
| Speed Grade | — | C5 (commercial, -5 speed) |
| High-Speed Transceivers | — | Up to 20 channels, up to 6.375 Gbps |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |
| PLLs | — | [DATA_NEEDED: PLL count] |
| Configuration Modes | — | Passive Serial, Fast Passive Parallel, JTAG |
| Lead-Free / RoHS | — | Lead-free per JEDEC MS-034AAU-1 |