EP3C5E144A7N vs EP3C5E144C7N Vergleich
Detaillierter Direktvergleich von EP3C5E144A7N von Altera und EP3C5E144C7N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP3C5E144A7N | EP3C5E144C7N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $22,80 | $13,17 |
| Series | Cyclone III | — |
| Logic Elements (LE) | 5,136 | 5,136 |
| Total Memory Bits | 423,936 bits (414 Kbits) | 423,936 |
| Embedded Memory Blocks | 46 x M9K (9 Kbit each) | — |
| Embedded 18x18 Multipliers | 23 | 46 |
| User I/O Pins | 94 | — |
| Number of I/O Banks | 4 | — |
| Number of PLLs | 4 | — |
| Core Voltage (VCCINT) | 1.2 V | — |
| I/O Bank Voltage (VCCIO) | Per-bank, supports 1.2 V to 3.3 V | — |
| Gehäuse | 144-LQFP Exposed Pad (EQFP, 22x22 mm) | 144-LQFP Exposed Pad (EQFP-144), 22x22 mm, 0.5 mm pitch |
| Speed Grade | 7 | C7 (7 ns delay) |
| Temperature Grade | Commercial (0C to +85C junction) | — |
| Process Technology | 65 nm low-k dielectric | TSMC 65 nm low-power |
| Configuration Modes | AS, PS, JTAG, Fast Passive Parallel | AS, PS, FPP, JTAG |
| Design Toolchain | Quartus II / Quartus Prime | — |
| Supported I/O Standards | LVDS, SSTL, LVTTL, PCI, LVCMOS | — |
| Montageart | Surface Mount | — |
| RoHS-Status | Compliant (per DigiKey product page) | Compliant |
| Device Family | — | Cyclone III |
| Logic Array Blocks (LAB) | — | 290 |
| Embedded M9K Memory Blocks | — | 46 |
| PLLs | — | 4 |
| User I/Os | — | 94 |
| Betriebs-Sperrschichttemperatur | — | 0C to +85C |
| I/O Standards | — | LVDS, SSTL, HSTL, LVCMOS, PCI/PCI-X |