EP3CLS70U484C7N vs EP3CLS100U484C7N Vergleich
Detaillierter Direktvergleich von EP3CLS70U484C7N von Intel und EP3CLS100U484C7N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP3CLS70U484C7N | EP3CLS100U484C7N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $128,10 | $412,65 |
| Family | Cyclone III LS | — |
| Logic Elements (LE) | 70,208 | — |
| Embedded Memory | 3,068,928 bits | 4,451,328 bits (4.4 Mbit) |
| Logic Array Blocks (LAB) | 4,388 | — |
| Maximum User I/O | 278 | — |
| Gehäuse | 484-FBGA (U484, 19x19 mm) | 484-ball FBGA (UBGA) |
| Process Technology | 65 nm CMOS | 65 nm TSMC low-power |
| Core Supply Voltage (VCCINT) | 1.2 V | — |
| Speed Grade | 7 (commercial) | 7 (commercial) |
| Betriebstemperatur | 0C to +85C (commercial) | 0C to +85C (commercial) |
| Embedded 18x18 Multipliers | 198 | — |
| PLLs | 4 | [DATA_NEEDED: PLL count] |
| Global Clock Networks | 8 | — |
| Configuration Modes | AS, AP, PS, JTAG | — |
| Memory Interface Support | DDR/DDR2/QDRII+ SRAM | — |
| RoHS-Status | Compliant | Compliant |
| Montageart | Surface Mount | Surface Mount (BGA) |
| Device Family | — | Cyclone III LS |
| Logic Elements | — | 100,448 |
| User I/O Pins | — | 278 |
| Core Supply Voltage | — | 1.2 V |
| Maximum Internal Frequency | — | 437.5 MHz |
| Configuration Mode | — | AS / AP / PS / JTAG |
| DSP Blocks (18x18 multipliers) | — | [DATA_NEEDED: DSP block count] |
| I/O Banks | — | 8 |
| Lead-Free | — | Yes |