EP3SE260H780C3N vs EP3SE260H780C4LG Vergleich
Detaillierter Direktvergleich von EP3SE260H780C3N von Intel und EP3SE260H780C4LG von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP3SE260H780C3N - Stratix III E FPGA, 255K LE, 780-BGA | Intel / Altera
EP3SE260H780C3N ✓ Aktiv
Spezifikationsvergleich
| Parameter | EP3SE260H780C3N | EP3SE260H780C4LG |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $1.325,00 | $1.290,00 |
| Series | Stratix® III E | — |
| Logic Elements (LE) | 255,000 | — |
| Embedded Memory (bits) | 16,672,768 | — |
| Number of LABs/CLBs | 10,200 | — |
| User I/Os | 488 | — |
| Number of Pins / Balls | 780 | — |
| Gehäuse | 780-BBGA, FCBGA (H780) | 780-ball FineLine BGA (HBGA, 29 mm x 29 mm, 1.0 mm pitch) |
| Montageart | Surface Mount | Surface Mount (BGA) |
| Betriebstemperatur | 0 °C to +85 °C (C grade, commercial) | — |
| Process Technology | 40 nm CMOS | 65 nm TSMC low-power CMOS |
| Maximum Core Frequency | [DATA_NEEDED: maximum core frequency MHz] | — |
| Supply Voltage (VCCINT) | [DATA_NEEDED: VCCINT nominal V] | — |
| Transceivers | [DATA_NEEDED: number of embedded transceivers and max data rate] | — |
| DSP Blocks | [DATA_NEEDED: number of DSP blocks and precision] | — |
| RoHS-Status | Compliant (lead-free 'N' suffix) | Compliant (Pb-free HBGA) |
| Feuchtigkeitsempfindlichkeitsgrad (MSL) | [DATA_NEEDED: MSL level per JEDEC J-STD-020] | — |
| Configuration Method | SRAM-based, configured via JTAG / passive / active serial / fast passive parallel | — |
| Design Toolchain | Altera Quartus II (legacy); Intel Quartus Prime | — |
| Family | — | Stratix III Enhanced (EP3SE) |
| Logic Elements | — | 254,400 |
| Adaptive Logic Modules (ALMs) | — | 101,760 |
| Embedded Memory (M9K + M144K) | — | 18.36 Mbits |
| DSP Blocks (18-bit x 18-bit) | — | 768 |
| 18-bit x 18-bit Multipliers | — | 1,536 |
| Transceivers (full-duplex) | — | 8 (up to 6.375 Gbps) |
| Maximum User I/O Pins | — | 488 |
| Speed Grade | — | C4 (commercial, mid-speed tier) |
| Temperature Grade | — | Commercial (0C to +85C junction) |
| Operating Voltage (Core) | — | 0.9 V / 1.0 V / 1.1 V (programmable) |
| External Memory Interface | — | Up to 800 Mbps DDR3, QDR II+, RLDRAM II |
| Hard IP Blocks | — | PCIe Gen2, 10GbE MAC, memory controllers |
| MSL-Level | — | 3 (per JEDEC J-STD-020) |