EP3SE260H780C3N vs EP3SE260H780C4LN Vergleich
Detaillierter Direktvergleich von EP3SE260H780C3N von Intel und EP3SE260H780C4LN von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP3SE260H780C3N - Stratix III E FPGA, 255K LE, 780-BGA | Intel / Altera
EP3SE260H780C3N ✓ AktivIntel
EP3SE260H780C4LN - Stratix III E FPGA 255K LE 780-FCBGA | Intel
EP3SE260H780C4LN ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP3SE260H780C3N | EP3SE260H780C4LN |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $1.325,00 | $11.950,00 |
| Series | Stratix® III E | — |
| Logic Elements (LE) | 255,000 | — |
| Embedded Memory (bits) | 16,672,768 | — |
| Number of LABs/CLBs | 10,200 | — |
| User I/Os | 488 | — |
| Number of Pins / Balls | 780 | — |
| Gehäuse | 780-BBGA, FCBGA (H780) | 780-ball FCBGA (FineLine BGA) |
| Montageart | Surface Mount | — |
| Betriebstemperatur | 0 °C to +85 °C (C grade, commercial) | 0C to +85C (commercial) |
| Process Technology | 40 nm CMOS | — |
| Maximum Core Frequency | [DATA_NEEDED: maximum core frequency MHz] | — |
| Supply Voltage (VCCINT) | [DATA_NEEDED: VCCINT nominal V] | — |
| Transceivers | [DATA_NEEDED: number of embedded transceivers and max data rate] | — |
| DSP Blocks | [DATA_NEEDED: number of DSP blocks and precision] | — |
| RoHS-Status | Compliant (lead-free 'N' suffix) | Compliant |
| Feuchtigkeitsempfindlichkeitsgrad (MSL) | [DATA_NEEDED: MSL level per JEDEC J-STD-020] | — |
| Configuration Method | SRAM-based, configured via JTAG / passive / active serial / fast passive parallel | — |
| Design Toolchain | Altera Quartus II (legacy); Intel Quartus Prime | — |
| Family | — | Stratix III E |
| Logic Elements | — | 255,000 |
| Embedded Memory | — | 16,672,768 bits (16.67 Mbit) |
| Logic Array Blocks (LABs) | — | 10,200 |
| Embedded Multipliers (18x18) | — | 384 |
| User I/O Count | — | 488 |
| Speed Grade | — | C4 (commercial, moderate speed) |
| Core Voltage (VCC) | — | 1.0 V |
| I/O Voltage (VCCIO) | — | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-dependent) |
| Auxiliary Voltage (VCCPD/VCCPT) | — | 2.5 V / 3.0 V |
| PLLs | — | 8 |
| Global Clock Networks | — | 16 |
| Process Node | — | 40 nm TSMC |
| Configuration Modes | — | FPP, AS, PS, JTAG |
| MSL-Level | — | 3 (168 hours) |