EP3SE50F484I4LN vs EP3SE50F484I4L Vergleich

Detaillierter Direktvergleich von EP3SE50F484I4LN von Intel und EP3SE50F484I4L von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Intel
EP3SE50F484I4L EP3SE50F484I4L - Stratix III E FPGA, 47.5K LE, 484-FBGA | Intel

EP3SE50F484I4L - Stratix III E FPGA, 47.5K LE, 484-FBGA | Intel

EP3SE50F484I4L ⚠ Letzte Bestellmöglichkeit

Spezifikationsvergleich

Parameter EP3SE50F484I4LN EP3SE50F484I4L
Marke Intel Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Letzte Kaufgelegenheit
Lagerstatus In Stock In Stock
Stückpreis (USD) $895,00 $1.290,00
Family Stratix III E Stratix III E
Logic Elements (LE) 47,500 47,500
Logic Array Blocks (LABs) 1,900 1,900
Embedded Memory 5.76 Mbit (estimated from 47.5K LE family) 5,760 Kbit (5.625 Mbit)
User I/O Count 296 —
Process Node 65 nm 40 nm CMOS
Core Voltage (VCCINT) 0.9 V —
Auxiliary Voltage (VCCAUX) 1.1 V —
I/O Voltage (VCCIO) 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.0 V (bank-dependent) —
Gehäuse 484-ball FBGA (FineLine BGA) 484-ball FCBGA (FBGA-484)
Pin/Pitch 484 balls, 1.0 mm pitch —
Betriebstemperatur -40C to +100C (industrial I4 grade) —
Configuration SRAM-based (external flash/EPCS required) —
RoHS-Status Compliant (LN suffix indicates lead-free) Compliant
Lead-Free Yes (LF / N suffix indicates lead-free) —
Transceivers 0 (F484 package does not include transceiver banks) —
PLL Count Up to 12 (estimated for Stratix III E family) —
DSP Blocks (18x18 Multipliers) [DATA_NEEDED: DSP block count] —
Design Tool Quartus II (legacy, support via Altera/Intel subscription) —
Adaptive Logic Modules (ALMs) — [DATA_NEEDED: ALM count]
Embedded Multipliers (18x18) — 384
Maximum User I/O — 296
Maximum Core Clock — 717 MHz (per third-party listing)
Speed Grade — 4 (slowest)
Betriebstemperaturbereich — Industrial (I): -40C to +100C junction
Montageart — Surface Mount (BGA)
Versorgungsspannung — Multiple rails: core 0.9V, I/O 1.2V-3.3V (per Stratix III handbook)
Configuration Method — Quartus II / EPCS serial / parallel
Lead-Free (Pb-free) — Yes (L suffix)
MSL-Level — MSL3 (per JEDEC J-STD-020, typical for FBGA-484)

Datenblätter & Ressourcen

Alle Produkte durchsuchen BOM erstellen Angebot anfordern