EP3SE50F780I3N vs EP3SE110F780I3N Vergleich
Detaillierter Direktvergleich von EP3SE50F780I3N von Intel und EP3SE110F780I3N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP3SE50F780I3N - Stratix III E FPGA, 47.5K Logic Elements, 780-FBGA | Intel
EP3SE50F780I3N ⚠ Letzte BestellmöglichkeitIntel
EP3SE110F780I3N - 107.5K Logic Elements, 780-FBGA FPGA | Intel Stratix III E
EP3SE110F780I3N NrndSpezifikationsvergleich
| Parameter | EP3SE50F780I3N | EP3SE110F780I3N |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $1.550,00 | $1.950,00 |
| Manufacturer | Intel (formerly Altera) | — |
| Family | Stratix III E | Stratix III E |
| Logic Elements | 47,500 | 107,500 |
| Embedded Memory Bits | 5,760,000 bits | 8,936,448 (approximately 1.1 MB) |
| User I/O Pins | 488 | — |
| Gehäuse | 780-ball FC-FBGA (Fine-pitch Chip-Scale BGA) | 780-pin FC-FBGA (Flip-Chip FineLine BGA) |
| Process Technology | 65 nm | 65 nm CMOS |
| Core Voltage | 0.9 V | 1.1 V (range 1.05 V to 1.15 V) |
| Operating Temperature Grade | Industrial | — |
| Configuration Interface | JTAG IEEE Std. 1149.1 (BST), Passive Serial, Fast Passive Parallel, Active Serial | Passive Serial (PS), Fast Passive Parallel (FPP), JTAG (IEEE 1149.1) |
| Boundary-Scan Support | Yes (IEEE 1149.1) | — |
| Montageart | Surface Mount | Surface Mount (BGA) |
| RoHS-Status | Compliant | Compliant |
| Lebenszyklusstatus | Last Time Buy (Stratix III family EOL announced) | — |
| Supply Type | Tray (per JAK Electronics listing) | — |
| Logic Array Blocks (LABs) | — | 4,300 |
| Maximum User I/Os | — | 488 |
| Betriebstemperatur | — | -40 °C to +100 °C (Industrial, "I" grade) |
| Boundary-Scan Test | — | Yes, per IEEE Std. 1149.1 |
| Speed Grade | — | 3 (Fast) |
| PLLs | — | Yes, with global and regional clock networks |
| MSL-Level | — | [DATA_NEEDED: MSL level] |
| Supply Voltage Tolerance | — | 1.05 V to 1.15 V |