EP3SL340H1152C3 vs EP3SL340H1152C4L Vergleich
Detaillierter Direktvergleich von EP3SL340H1152C3 von Intel und EP3SL340H1152C4L von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP3SL340H1152C3 | EP3SL340H1152C4L |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $2.550,00 | $3.500,00 |
| Family | Stratix III L | — |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements (Cells) | 337,500 | — |
| LABs | 13,500 | — |
| Maximum User I/O Pins | 744 | — |
| Total Internal Memory Bits | 18,822,144 | — |
| Core Supply Voltage (VccINT) | 1.1 V | — |
| Core Fabric Frequency | 717 MHz | — |
| Process Technology | 65 nm CMOS | 65 nm |
| Gehäuse | 1152-ball FCBGA (HBGA) | 1152-BBGA, FCBGA (HBGA) |
| Montageart | Surface Mount (BGA) | Surface Mount (BGA) |
| Operating Temperature Grade | Commercial (0C to +85C) | — |
| Speed Grade | C3 | C4L (L-suffix low power) |
| RoHS-Status | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS compliance] |
| Configuration Method | JTAG / Passive Parallel / Active Serial / Configuration Flash | — |
| Series | — | Stratix III L |
| Logic Elements | — | 337,500 |
| Embedded Memory Bits | — | 18,822,144 |
| Maximum User I/O | — | 744 |
| Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Embedded 18x18 Multipliers | — | 384 (per family datasheet) |
| Core Voltage (VCCINT) | — | 1.1 V |
| Betriebstemperatur | — | 0 C to +85 C (commercial) |
| MSL-Level | — | [DATA_NEEDED: MSL rating] |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED: lead-free status] |
| Configuration Memory | — | SRAM-based, volatile (needs external config device) |
| Maximum Operating Frequency | — | [DATA_NEEDED: per design, ~450 MHz logic per GlobalSpec listing] |
| I/O Standards Supported | — | LVDS, LVTTL, LVCMOS, SSTL, HSTL (per family) |