EP3SL50F484C3 vs EP3SL50F484C4L Vergleich
Detaillierter Direktvergleich von EP3SL50F484C3 von Intel und EP3SL50F484C4L von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP3SL50F484C3 | EP3SL50F484C4L |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Obs |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $651,25 |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Family | Stratix III L | Stratix III L |
| Logic Cells | 47,500 cells | — |
| Technology | 65 nm | — |
| Listed Frequency | 500 MHz | — |
| Internal Frequency | 800 MHz | — |
| Versorgungsspannung | 1.1 V | — |
| Logic Array Blocks | 1,900 LABs | — |
| User I/O | 296 I/Os | — |
| Gehäuse | 484-pin FC-FBGA | 484-ball FBGA (FineLine BGA) |
| Pin-Anzahl | 484 pins | — |
| Package Type | FBGA-484 | — |
| Betriebstemperatur | 0 °C to 85 °C | — |
| Device Category | Programmable logic IC | — |
| Montageart | Surface Mount | Surface Mount |
| Manufacturer Technology Description | 65-nm low-power high-performance FPGA | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | Compliant |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Halogen-Free Status | [DATA_NEEDED: halogen-free status] | — |
| Package Dimensions | [DATA_NEEDED: package dimensions] | — |
| Configuration Memory | [DATA_NEEDED: configuration memory size] | — |
| Embedded Transceivers | [DATA_NEEDED: embedded transceiver count] | — |
| Power Consumption | [DATA_NEEDED: power consumption] | — |
| Logic Elements (LE) | — | 47,500 |
| Logic Array Blocks (LABs) | — | 1,900 |
| User I/O Count | — | 296 |
| Total RAM Bits | — | 2,184,192 |
| Core Voltage | — | 0.9 V |
| Process Technology | — | 65 nm CMOS |
| Betriebstemperaturbereich | — | 0°C to 85°C (commercial) |
| Maximum Fabric Frequency | — | [DATA_NEEDED: maximum fabric frequency] |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |
| Transceivers | — | [DATA_NEEDED: number of transceivers] |
| MSL-Level | — | 3 (per JEDEC J-STD-020) |
| Design Software | — | Quartus II |
| Architecture | — | Adaptive Logic Module (ALM) |