EP3SL50F484I4LN vs EP3SL50F484I4LG Vergleich
Detaillierter Direktvergleich von EP3SL50F484I4LN von Altera und EP3SL50F484I4LG von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP3SL50F484I4LG - Stratix III L FPGA, 47.5K LE, 484-FCBGA | Altera (Intel)
EP3SL50F484I4LG NrndSpezifikationsvergleich
| Parameter | EP3SL50F484I4LN | EP3SL50F484I4LG |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $945,00 |
| Product Type | Field Programmable Gate Array (FPGA) | — |
| Device Family | Stratix III L | — |
| Logic Cells | 47,500 | — |
| Embedded Memory | 2,184,192 bits | 2,184,192 bits (273 KB) |
| User I/O | 296 | — |
| Logic Array Blocks | 1,900 LABs | — |
| Listed Frequency | 717 MHz | — |
| Process Technology | CMOS | — |
| Gehäuse | 484-BBGA, FCBGA | 484-Ball FCBGA (FBGA) |
| Package Description | FBGA-484 | — |
| Terminal Count | 484 | — |
| Terminal Form | Ball | — |
| Package Body Material | Plastic/Epoxy | — |
| Lead-Free Status | Lead free | — |
| Operating Temperature Grade | Industrial | — |
| I/O Banks | [DATA_NEEDED: I/O bank count] | — |
| Transceiver Count | [DATA_NEEDED: transceiver count] | — |
| Core Voltage | [DATA_NEEDED: core voltage] | — |
| I/O Voltage | [DATA_NEEDED: I/O voltage] | — |
| Junction Temperature | [DATA_NEEDED: junction temperature] | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | Compliant |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Family | — | Stratix III L |
| Series | — | EP3SL50 |
| Logic Elements | — | 47,500 |
| User I/Os | — | 296 |
| Montageart | — | Surface Mount |
| Betriebstemperatur | — | -40C to +100C (Industrial) |
| Speed Grade | — | I4 (fast) |
| Versorgungsspannung | — | 0.85 V / 1.1 V / 1.2 V / 2.5 V / 3.3 V (multi-rail) |
| Process Node | — | 40 nm |
| Lead-Free | — | Yes |
| Total I/O Banks | — | [DATA_NEEDED: I/O bank count] |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |
| Transceivers | — | [DATA_NEEDED: transceiver channel count] |
| Configuration Memory | — | SRAM-based |
| Configuration Interface | — | JTAG / Passive Serial / Fast Passive Parallel |