EP4CE6F17I8L vs EP4CE6F17C7N Vergleich
Detaillierter Direktvergleich von EP4CE6F17I8L von Altera und EP4CE6F17C7N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP4CE6F17I8L | EP4CE6F17C7N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $17,25 | $3,60 |
| Series | Cyclone IV E | Cyclone IV E |
| Logic Elements | 6,272 | — |
| Total Memory Bits | 276,480 | — |
| Number of Logic Array Blocks | 392 | — |
| Embedded Multipliers (18x18) | 15 | — |
| User I/O Pins | 179 | — |
| Number of I/O Banks | 8 | — |
| Number of PLLs | 2 | — |
| Supply Voltage (Core) | 1.2 V | — |
| Betriebstemperaturbereich | -40C to +100C (Industrial) | — |
| Gehäuse | 256-LBGA (FBGA-256, 17x17 mm, 1.0 mm pitch) | — |
| Montageart | Surface Mount | Surface Mount |
| Configuration Method | JTAG, Active Serial (AS), Passive Serial (PS) | — |
| Process Technology | 60 nm low-power CMOS | 60 nm |
| RoHS-Status | Compliant | — |
| MSL-Level | 3 (168 hours) | — |
| Manufacturer | — | Altera / Intel |
| Product Category | — | FPGA - Field Programmable Gate Array |
| Number of Logic Elements / Cells | — | 6272 |
| Number of CLBs / LABs | — | 392 |
| Total RAM Bits | — | 276480 bits |
| Number of User I/O | — | 179 |
| Gehäuse / Bauform | — | 256-LBGA (FBGA-256) |
| Package Body Size | — | 17 mm x 17 mm |
| Ball Pitch | — | 1 mm |
| Core Supply Voltage | — | 1.2 V |
| Maximum Internal Clock Frequency | — | 472.5 MHz |
| Lead-Free Finish | — | Yes (N suffix) |
| Number of Terminations | — | 256 |
| RoHS Compliance | — | Compliant |
| Lebenszyklusstatus | — | Active production |
| Operating Temperature Grade | — | [DATA_NEEDED: exact C-grade junction/ambient temperature range from Cyclone IV datasheet] |
| On-Chip PLL Count | — | [DATA_NEEDED: number of PLLs] |