EP4SGX530KF43C4 vs EP4SGX530KF43C3 Vergleich
Detaillierter Direktvergleich von EP4SGX530KF43C4 von Intel und EP4SGX530KF43C3 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP4SGX530KF43C3 - Stratix IV GX FPGA, 531K LE, 1760-BGA | Intel
EP4SGX530KF43C3 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP4SGX530KF43C4 | EP4SGX530KF43C3 |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $3.725,00 | $3.700,00 |
| Device Type | FPGA - Field Programmable Gate Array | — |
| Series | Stratix IV GX | — |
| Logic Elements | 531,200 | 531,200 |
| Logic Array Blocks (LABs) | 21,248 | — |
| Embedded Memory | 28,033,024 bits | 28,033,024 bits (approximately 27.4 Mbits / 3,424 Kbits per block RAM array) |
| User I/Os | 880 | — |
| Gehäuse | 1760-ball FC-BGA (42.5 x 42.5 mm) | 1760-ball FC-FBGA (KF43) |
| Process Technology | 40 nm | 40 nm |
| Core Voltage | 0.9 V | — |
| Internal Fabric Clock | 800 MHz (max) | — |
| Transceivers | Up to 24 channels, 8.5 Gbps | — |
| Betriebstemperatur | 0 C to +85 C (Commercial) | — |
| Montageart | Surface Mount (BGA) | Surface Mount (flip-chip BGA) |
| RoHS-Status | Compliant | Compliant (Pb-free) |
| Lead Free | Yes | — |
| Family | — | Stratix IV GX |
| Adaptive Logic Modules (ALMs) | — | [DATA_NEEDED: ALM count] |
| DSP Blocks (18x18 multipliers) | — | 880 |
| Maximum User I/O Pins | — | [DATA_NEEDED: pin count from KF43 BGA map] |
| Number of Transceivers | — | 24 (up to 8.5 Gbps per channel) |
| PLLs | — | 8 |
| PCIe Hard IP Blocks | — | 4 (Gen1/Gen2 capable) |
| Core Voltage (VCC) | — | 0.9 V |
| Speed Grade | — | C3 |
| Betriebstemperaturbereich | — | 0C to +85C (commercial, 'C' suffix) |
| Configuration Method | — | Active serial (EPCS), passive serial, JTAG, Fast Passive Parallel |
| MSL-Level | — | 3 (per JEDEC J-STD-020) |