EP610DC-15 vs EP610DI-25 Vergleich
Detaillierter Direktvergleich von EP610DC-15 von Altera und EP610DI-25 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610DC-15 | EP610DI-25 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,95 | $9,95 |
| Product Family | Classic EPLD (EP610) | — |
| Architecture | UV-erasable CMOS PAL-type | — |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 | — |
| Dedicated Inputs | 20 | 4 |
| Bidirectional I/O Pins | 16 | — |
| Total Product Terms | 160 | — |
| Propagation Delay (tPD) | 15 ns (speed grade -15) | 25 ns |
| Maximum Internal Clock Frequency | 71.4 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V nominal |
| Betriebstemperatur | 0C to 70C (commercial) | Industrial (per "I" suffix) |
| Gehäuse | 24-pin Ceramic DIP (CDIP-24) with UV window | — |
| Montageart | Through-Hole | Through-Hole (DIP) |
| Programming Method | JEDEC fuse map, UV erasure | — |
| Technology | CMOS | CMOS EPROM (UV-erasable) |
| RoHS-Status | [DATA_NEEDED: RoHS status] | — |
| Part Family | — | Classic EPLD |
| Maximum Pipelined Clock Frequency | — | 100 MHz (max fCNT, per family datasheet) |
| I/O Pins | — | 16 (bidirectional) |
| Total User I/O | — | 20 |
| Package Type | — | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 |
| Pin-Anzahl | — | 24 |
| Speed Grade Suffix | — | 25 = 25 ns |
| Compliance | — | RoHS status unknown (legacy 1990s part) |