EP610DC35 vs EP610DC15 Vergleich
Detaillierter Direktvergleich von EP610DC35 von Altera und EP610DC15 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610DC35 | EP610DC15 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $19,20 | $7,50 |
| Family | Classic EPLD | EP610 Classic EPLD |
| Logic Elements | 16 macrocells | — |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 35 ns | 15 ns |
| Maximum Frequency | 28.6 MHz | — |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| Versorgungsspannung | 5 V | — |
| Gehäuse | 24-pin CDIP (Ceramic DIP) with quartz erase window | 24-pin CDIP (Ceramic DIP, windowed) |
| Montageart | Through-Hole | Through-Hole |
| Pin-Anzahl | 24 | — |
| Technology | UV-erasable CMOS EPROM | CMOS |
| Programming Method | Altera legacy programmer (PLDLMax or compatible) | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | 0C to +70C |
| RoHS-Status | [DATA_NEEDED: RoHS status] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| I/O Pins | [DATA_NEEDED: number of user I/O pins] | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 16 |
| Architecture | — | PAL-type |
| Maximum Clock Frequency (fMAX) | — | 71.4 MHz |
| Total Inputs | — | 20 |
| I/O Lines | — | 16 |
| Product Terms | — | 160 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Reprogrammability | — | Yes (UV erasable via windowed package) |