EP610DI-30 vs EP610DC-15 Vergleich
Detaillierter Direktvergleich von EP610DI-30 von Rochester Electronics und EP610DC-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Rochester Electronics
EP610DI-30 - 16-Macrocell Classic EPLD, 30ns, CERDIP-24 | Rochester Electronics
EP610DI-30 ✓ Aktiv
Spezifikationsvergleich
| Parameter | EP610DI-30 | EP610DC-15 |
|---|---|---|
| Marke | Rochester Electronics | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $23,50 | $7,95 |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Classic EP610 | — |
| Macrocells | 16 | 16 |
| Propagation Delay (tPD) | 30 ns | 15 ns (speed grade -15) |
| Pipelined Data Rate | 100 MHz | — |
| Technology | CMOS | CMOS |
| Versorgungsspannung | 5 V (single supply) | — |
| Gehäuse | CERDIP-24 (windowed, UV-erasable) | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Montageart | Through-Hole | Through-Hole |
| Programmable Elements | EPROM (UV-erasable, windowed) | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | 0C to 70C (commercial) |
| I/O Pins | [DATA_NEEDED: I/O pin count] | — |
| Logic Capacity | [DATA_NEEDED: usable gates / logic capacity] | — |
| RoHS-Status | unknown | [DATA_NEEDED: RoHS status] |
| Lead-Free | unknown | — |
| Original Manufacturer | Altera (now Intel) | — |
| Current Supplier | Rochester Electronics (authorized continuing source) | — |
| MSL-Level | N/A (through-hole, non-surface-mount) | — |
| Product Family | — | Classic EPLD (EP610) |
| Architecture | — | UV-erasable CMOS PAL-type |
| Logic Expanders | — | 4 |
| Dedicated Inputs | — | 20 |
| Bidirectional I/O Pins | — | 16 |
| Total Product Terms | — | 160 |
| Maximum Internal Clock Frequency | — | 71.4 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Programming Method | — | JEDEC fuse map, UV erasure |