EP610DI-30N vs EP610DC-25 Vergleich
Detaillierter Direktvergleich von EP610DI-30N von Altera und EP610DC-25 von Rochester Electronics. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ AktivSpezifikationsvergleich
| Parameter | EP610DI-30N | EP610DC-25 |
|---|---|---|
| Marke | Altera | Rochester Electronics |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $17,80 | $9,95 |
| Product Type | EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EP610 | Altera Classic EPLD |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 30 ns | — |
| Maximum Frequency | 33.3 MHz (system); 100 MHz (pipelined) | — |
| Supply Voltage (VCC) | 5 V ±5% | 4.75 V to 5.25 V (5 V nominal) |
| Gehäuse | CDIP-24 (Ceramic DIP, windowed) | 24-pin CDIP (Ceramic DIP, through-hole) |
| Pin-Anzahl | 24 | — |
| Betriebstemperatur | -40°C to +85°C (industrial) | 0 C to +70 C |
| Process Technology | CMOS | — |
| Programming Method | UV-erasable (windowed ceramic) | JEDEC fuse-map / UV-erase |
| Montageart | Through-hole (DIP) | Through Hole |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | — |
| Equivalent Gates | — | 300 |
| Maximum Propagation Delay (tPD) | — | 25 ns |
| Pipelined Data Rate | — | Up to 100 MHz |
| Number of I/O Pins | — | 22 |
| Number of Dedicated Inputs | — | 4 |
| Total Pin Count | — | 24 |
| Technology | — | CMOS EPROM (UV-erasable) |
| Speed Grade Suffix | — | -25 (25 ns tPD) |