EP610DI-30N vs EP610DC-30 Vergleich
Detaillierter Direktvergleich von EP610DI-30N von Altera und EP610DC-30 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610DI-30N | EP610DC-30 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $17,80 | $10,40 |
| Product Type | EPLD (Erasable Programmable Logic Device) | Classic EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EP610 | EP610 (Classic Device Family) |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 30 ns | 30 ns |
| Maximum Frequency | 33.3 MHz (system); 100 MHz (pipelined) | — |
| Supply Voltage (VCC) | 5 V ±5% | — |
| Gehäuse | CDIP-24 (Ceramic DIP, windowed) | 24-pin CERDIP (windowed) |
| Pin-Anzahl | 24 | — |
| Betriebstemperatur | -40°C to +85°C (industrial) | Commercial (0C to +70C) |
| Process Technology | CMOS | — |
| Programming Method | UV-erasable (windowed ceramic) | — |
| Montageart | Through-hole (DIP) | Through-Hole |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | — |
| Logic Expanders | — | 4 (4 product terms per macrocell) |
| Maximum Pipelined Clock Frequency | — | 100 MHz |
| Dedicated Inputs | — | 16 |
| I/O Pins | — | 16 (with output enable) |
| Speed Grade | — | -30 (30 ns tPD) |
| Technology | — | CMOS EPROM |
| Programmability | — | UV-erasable, windowed EPROM |
| Security Bit | — | Yes (protects design after programming) |
| Output Modes | — | Registered and Combinatorial |