EP610DI-30N vs EP610DI-25 Vergleich
Detaillierter Direktvergleich von EP610DI-30N von Altera und EP610DI-25 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610DI-30N | EP610DI-25 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $17,80 | $9,95 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EP610 | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 30 ns | 25 ns |
| Maximum Frequency | 33.3 MHz (system); 100 MHz (pipelined) | — |
| Supply Voltage (VCC) | 5 V ±5% | 5 V nominal |
| Gehäuse | CDIP-24 (Ceramic DIP, windowed) | — |
| Pin-Anzahl | 24 | 24 |
| Betriebstemperatur | -40°C to +85°C (industrial) | Industrial (per "I" suffix) |
| Process Technology | CMOS | — |
| Programming Method | UV-erasable (windowed ceramic) | — |
| Montageart | Through-hole (DIP) | Through-Hole (DIP) |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | — |
| Part Family | — | Classic EPLD |
| Maximum Pipelined Clock Frequency | — | 100 MHz (max fCNT, per family datasheet) |
| I/O Pins | — | 16 (bidirectional) |
| Dedicated Inputs | — | 4 |
| Total User I/O | — | 20 |
| Technology | — | CMOS EPROM (UV-erasable) |
| Package Type | — | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 |
| Speed Grade Suffix | — | 25 = 25 ns |
| Compliance | — | RoHS status unknown (legacy 1990s part) |