EP610ILC-10 vs EP610DC-20 Vergleich
Detaillierter Direktvergleich von EP610ILC-10 von Altera und EP610DC-20 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610ILC-10 | EP610DC-20 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,20 | $15,85 |
| Device Family | Classic EPLD | — |
| Product Type | UV-Erasable / OTP PLD | CMOS UV-Erasable Programmable Logic Device (EPLD) |
| Architecture | PAL-type with macrocells | — |
| Macrocells | 16 | — |
| Usable Gates | 300 | — |
| Product Terms | 160 | — |
| I/O Pins | 16 | 16 (bidirectional) |
| Dedicated Inputs | 4 | 4 |
| Versorgungsspannung | 5 V (single supply) | — |
| Pin-to-Pin Delay (tPD) | 10 ns (grade -10) | — |
| Counter Frequency (fCNT) | 100 MHz | — |
| Logic Family Compatibility | TTL (5 V CMOS/TTL-compatible I/O) | — |
| Gehäuse | PLCC-28 (plastic J-lead chip carrier) | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Montageart | Surface Mount (PLCC socket or solder) | Through-hole |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | 0 °C to 70 °C (commercial) |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance status] |
| Family | — | Classic EP610 |
| Logic Macrocells | — | 16 |
| Total Usable Pins | — | 20 |
| Product Terms (p-terms) | — | 160 |
| Propagation Delay (tPD) | — | 22 ns |
| Maximum Toggle Frequency (fMAX) | — | 55.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Programming Method | — | UV erasure + parallel programmer |
| Process Technology | — | CMOS, UV-erasable floating gate |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |