EP610ILC-25 vs EP610DC-20 Vergleich
Detaillierter Direktvergleich von EP610ILC-25 von Altera und EP610DC-20 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610ILC-25 | EP610DC-20 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,85 | $15,85 |
| Family | Classic EPLD (EP610 series) | Classic EP610 |
| Device Type | EEPLD (Electrically Erasable PLD) | — |
| Usable Gates | 300 | — |
| Macrocells | 16 | — |
| Product Terms | 160 | — |
| Maximum Operating Frequency (fMAX) | 40 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (5 V nominal) |
| Nominal Supply Voltage | 5 V | — |
| Total Inputs | 20 | — |
| Dedicated Inputs | 4 | 4 |
| Bidirectional I/O Pins | 16 | — |
| Betriebstemperaturbereich | 0 C to +70 C (commercial) | — |
| Gehäuse | 28-pin PLCC (J-lead) | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Montageart | Surface Mount | Through-hole |
| Process Technology | CMOS, electrically erasable | CMOS, UV-erasable floating gate |
| Programming Method | In-system, electrically erasable | UV erasure + parallel programmer |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Product Type | — | CMOS UV-Erasable Programmable Logic Device (EPLD) |
| Logic Macrocells | — | 16 |
| I/O Pins | — | 16 (bidirectional) |
| Total Usable Pins | — | 20 |
| Product Terms (p-terms) | — | 160 |
| Propagation Delay (tPD) | — | 22 ns |
| Maximum Toggle Frequency (fMAX) | — | 55.6 MHz |
| Betriebstemperatur | — | 0 °C to 70 °C (commercial) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |