EP610ILC-25 vs EP610ILC10 Vergleich
Detaillierter Direktvergleich von EP610ILC-25 von Altera und EP610ILC10 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610ILC-25 | EP610ILC10 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,85 | $4,10 |
| Family | Classic EPLD (EP610 series) | Classic EPLD (EP610) |
| Device Type | EEPLD (Electrically Erasable PLD) | — |
| Usable Gates | 300 | — |
| Macrocells | 16 | — |
| Product Terms | 160 | 160 |
| Maximum Operating Frequency (fMAX) | 40 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Nominal Supply Voltage | 5 V | — |
| Total Inputs | 20 | — |
| Dedicated Inputs | 4 | 4 |
| Bidirectional I/O Pins | 16 | — |
| Betriebstemperaturbereich | 0 C to +70 C (commercial) | — |
| Gehäuse | 28-pin PLCC (J-lead) | 28-pin PLCC (J-Lead) |
| Montageart | Surface Mount | Surface Mount / Socket |
| Process Technology | CMOS, electrically erasable | — |
| Programming Method | In-system, electrically erasable | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | Unknown - verify with manufacturer |
| Logic Elements | — | 16 macrocells |
| Gates | — | 300 gates equivalent |
| I/O Lines | — | 16 |
| Propagation Delay (tPD) | — | 15 ns (10 ns speed grade) |
| Maximum Internal Frequency | — | 100 MHz |
| Betriebstemperatur | — | -40 C to +85 C (Industrial) |
| Technology | — | CMOS, UV-erasable / OTP |
| Architecture | — | PAL-type AND-OR-NOT |