EP610IPC-25 vs EP610ILC-25 Vergleich
Detaillierter Direktvergleich von EP610IPC-25 von Intel und EP610ILC-25 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610IPC-25 | EP610ILC-25 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,85 | $9,85 |
| Family | Classic EPLD (EP610) | Classic EPLD (EP610 series) |
| Architecture | PAL-type, CMOS, Erasable | — |
| Propagation Delay (tpd) | 25 ns (max) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Maximum Inputs | 20 | — |
| Maximum I/O Pins | 16 | — |
| Dedicated Outputs | 16 | — |
| Product Terms | 160 | 160 |
| Betriebstemperatur | 0 °C to +70 °C (Commercial) | — |
| Gehäuse | 24-pin PDIP (Plastic DIP) | 28-pin PLCC (J-lead) |
| Technology | CMOS, UV-erasable (windowless in IPC pkg) | — |
| TTL Compatibility | 100% TTL emulation | — |
| Montageart | Through-Hole | Surface Mount |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| RoHS-Status | Non-compliant (contains Pb, PDIP package) | [DATA_NEEDED: RoHS status] |
| Logic Capacity | Equivalent to ~24 standard 24-pin PALs | — |
| Device Type | — | EEPLD (Electrically Erasable PLD) |
| Usable Gates | — | 300 |
| Macrocells | — | 16 |
| Maximum Operating Frequency (fMAX) | — | 40 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 25 ns |
| Nominal Supply Voltage | — | 5 V |
| Total Inputs | — | 20 |
| Dedicated Inputs | — | 4 |
| Bidirectional I/O Pins | — | 16 |
| Betriebstemperaturbereich | — | 0 C to +70 C (commercial) |
| Process Technology | — | CMOS, electrically erasable |
| Programming Method | — | In-system, electrically erasable |