EP610IPC-25 vs EP610IPC-10 Vergleich
Detaillierter Direktvergleich von EP610IPC-25 von Intel und EP610IPC-10 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610IPC-25 | EP610IPC-10 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,85 | $16,40 |
| Family | Classic EPLD (EP610) | Altera Classic EPLD |
| Architecture | PAL-type, CMOS, Erasable | Turbo-only AND-OR-NOT, PAL-type |
| Propagation Delay (tpd) | 25 ns (max) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Maximum Inputs | 20 | — |
| Maximum I/O Pins | 16 | — |
| Dedicated Outputs | 16 | — |
| Product Terms | 160 | 160 total |
| Betriebstemperatur | 0 °C to +70 °C (Commercial) | -40C to +85C (industrial) |
| Gehäuse | 24-pin PDIP (Plastic DIP) | 24-pin PDIP (Plastic DIP) |
| Technology | CMOS, UV-erasable (windowless in IPC pkg) | CMOS EPROM (UV-erasable / OTP) |
| TTL Compatibility | 100% TTL emulation | — |
| Montageart | Through-Hole | — |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| RoHS-Status | Non-compliant (contains Pb, PDIP package) | — |
| Logic Capacity | Equivalent to ~24 standard 24-pin PALs | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Programmable Gates | — | 300 usable gates |
| Macrocells | — | 16 |
| Maximum Operating Frequency | — | 100 MHz |
| Propagation Delay (tPD) | — | 15 ns (commerical -10 grade) |
| Dedicated Inputs | — | 4 |
| I/O Pins | — | 16 |
| Total Input Pins | — | 20 |
| Versorgungsspannung | — | 5 V |
| Programming Method | — | Altera programming hardware (UV erase for I grade, OTP for C grade) |
| TTL Emulation | — | 100% TTL compatible |