EP610LC-25 vs EP610LC-30 Vergleich
Detaillierter Direktvergleich von EP610LC-25 von Intel und EP610LC-30 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610LC-25 | EP610LC-30 |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $6,20 | $16,40 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Classic EPLD | Classic EPLD (EP610) |
| Macrocells | 16 | — |
| Logic Array Blocks (LABs) | 4 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Toggle Frequency | 100 MHz | — |
| Pipelined Data Rate | Up to 100 MHz | up to 100 MHz |
| Versorgungsspannung | 5 V ±5% | — |
| Technology | CMOS | CMOS EPROM (UV-erasable) |
| Programmability | UV-erasable (windowed package) | — |
| Gehäuse | PLCC-28 | 24-pin CERDIP / PDIP |
| Betriebstemperatur | 0C to +70C (commercial) | 0 C to +70 C (commercial) / -55 C to +125 C (military) |
| Montageart | Surface Mount | Through-Hole |
| I/O Pins | [DATA_NEEDED: exact I/O count] | — |
| RoHS-Status | [DATA_NEEDED] | [DATA_NEEDED: RoHS status] |
| Macro Cells | — | 16 |
| Logic Gates | — | Equivalent to 300 gates (typical) |
| Pin-to-Pin Delay (tPD) | — | 30 ns |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Programming Voltage (VPP) | — | 13 V nominal |
| Erase/Program Cycles | — | 1000 typical |
| Ausgangstyp | — | CMOS tri-state (programmable) |
| Logic Compatibility | — | TTL and CMOS |
| Turbo Mode | — | Yes (registered path bypass) |