EP610LC-30 vs EP610JI-30 Vergleich

Detaillierter Direktvergleich von EP610LC-30 von Intel und EP610JI-30 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP610LC-30 EP610JI-30
Marke Intel Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $16,40 $9,40
Family Classic EPLD (EP610) Altera Classic EPLD (EP610)
Macro Cells 16 —
Logic Gates Equivalent to 300 gates (typical) —
Pin-to-Pin Delay (tPD) 30 ns —
Pipelined Data Rate up to 100 MHz Up to 100 MHz
Supply Voltage (VCC) 4.75 V to 5.25 V —
Programming Voltage (VPP) 13 V nominal —
Technology CMOS EPROM (UV-erasable) —
Gehäuse 24-pin CERDIP / PDIP CQCC28 (windowed ceramic JLCC, J-bend)
Betriebstemperatur 0 C to +70 C (commercial) / -55 C to +125 C (military) -40C to +85C (industrial, per EP610 family suffix convention)
Erase/Program Cycles 1000 typical —
Montageart Through-Hole Surface Mount (JLCC)
Ausgangstyp CMOS tri-state (programmable) —
RoHS-Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS]
Logic Compatibility TTL and CMOS —
Turbo Mode Yes (registered path bypass) —
Device Type — UV Erasable Programmable Logic Device (EPLD)
Macrocells — 16
Propagation Delay (tpd) — 30 ns (max)
Product Terms — 160
Dedicated Inputs — 4
I/O Pins — 16
External Clocks — 2
Versorgungsspannung — 5 V (single supply)
Process Technology — CMOS
Package Code — JLCC-28 / CQCC28
Erasure Method — Ultraviolet (UV) via top window
Programming — Altera Logic Programmer compatible
Lead-Free — [DATA_NEEDED: lead-free status]

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