EP610LI-30 vs EP610DC-30 Vergleich
Detaillierter Direktvergleich von EP610LI-30 von Rochester Electronics und EP610DC-30 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610LI-30 | EP610DC-30 |
|---|---|---|
| Marke | Rochester Electronics | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $18,50 | $10,40 |
| Product Type | EPLD (Erasable Programmable Logic Device) | Classic EPLD (Erasable Programmable Logic Device) |
| Family | Classic EPLD (MAX architecture) | EP610 (Classic Device Family) |
| Macrocells | 16 | 16 |
| Pin-to-Pin Delay (tPD) | 30 ns | — |
| Maximum Internal Frequency (fMAX) | 100 MHz (pipelined) | — |
| AND Array | 24V16 | — |
| Process Technology | CMOS, UV-erasable EPROM cells | — |
| Supply Voltage (VCC) | 5 V (TTL-compatible I/O) | — |
| Gehäuse | 24-pin Ceramic DIP (windowed, CDIP) | 24-pin CERDIP (windowed) |
| Betriebstemperatur | -55C to +125C (military/extended) | Commercial (0C to +70C) |
| Output Polarity | User-configurable per macrocell | — |
| Flip-Flop per Cell | D / T / J-K configurable | — |
| Programming Method | UV erase + Classic-series PLD programmer | — |
| RoHS-Status | unknown | — |
| Manufacturer | Rochester Electronics (originally Altera) | — |
| Logic Expanders | — | 4 (4 product terms per macrocell) |
| Usable Gates | — | 300 |
| Maximum Pipelined Clock Frequency | — | 100 MHz |
| Propagation Delay (tPD) | — | 30 ns |
| Dedicated Inputs | — | 16 |
| I/O Pins | — | 16 (with output enable) |
| Montageart | — | Through-Hole |
| Speed Grade | — | -30 (30 ns tPD) |
| Technology | — | CMOS EPROM |
| Programmability | — | UV-erasable, windowed EPROM |
| Security Bit | — | Yes (protects design after programming) |
| Output Modes | — | Registered and Combinatorial |