EP610PC-15 vs EP610PC-25T Vergleich
Detaillierter Direktvergleich von EP610PC-15 von Altera und EP610PC-25T von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP610PC-25T - 16-Macrocell Classic EPLD, 25ns, PDIP-24 | Intel / Altera
EP610PC-25T ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP610PC-15 | EP610PC-25T |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $17,50 | $28,95 |
| Family | Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | Erasable Programmable Logic Device (EPLD, OTP for plastic package) |
| Usable Gates | 300 gates | — |
| Macrocells | 16 | — |
| Logic Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) | — |
| Maximum Counter Frequency | 100 MHz (per family datasheet) | — |
| Pipelined Data Rate | Up to 100 MHz | up to 100 MHz |
| Supply Voltage (VCC) | 5 V (single supply) | 5 V |
| Technology | CMOS | — |
| Architecture | PAL-type, sum-of-products AND/OR array | — |
| TTL Emulation | 100% TTL compatible | — |
| Gehäuse | PDIP-24 (plastic DIP, 24-pin) | PDIP-24 (Plastic DIP, 24-pin, 0.300 in row spacing) |
| Pin-Anzahl | 24 pins | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | 0 °C to +70 °C (commercial) |
| Montageart | Through-Hole (DIP) | Through-hole |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Development Tool | Altera MAX+PLUS II | — |
| Logic Test Circuitry | On-board for AC/DC verification | — |
| Manufacturer | — | Intel (formerly Altera) |
| Distributor / Stocking Source | — | Rochester Electronics, LLC |
| Device Family | — | Altera Classic EPLD - EP610 |
| Logic Capacity | — | 300 usable gates |
| Macro Cells | — | 16 |
| Registers | — | 16 |
| User I/Os | — | 16 |
| Propagation Delay (tPD) | — | 25 ns (speed grade 25) |
| Maximum Toggle Frequency | — | [DATA_NEEDED: max fmax] |
| Process Technology | — | ECMOS (CMOS, EPROM-based) |
| Pinout Compatibility | — | Pin-compatible with EP610DC-25 (CERDIP-24, windowed) |
| Programming Method | — | OTP (one-time programmable) via Altera programming hardware |
| Shipping Form (T suffix) | — | Tube |