EP610PC-20 vs EP610PC-30 Vergleich
Detaillierter Direktvergleich von EP610PC-20 von Altera und EP610PC-30 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610PC-20 | EP610PC-30 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $47,80 | $27,74 |
| Family | Classic EPLD | — |
| Logic Elements | 16 macrocells | — |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 20 ns | 30 ns |
| Maximum Operating Frequency | 100 MHz (pipelined) | — |
| Supply Voltage (VCC) | 5 V ±10% | 5 V (4.75 V to 5.25 V) |
| Anzahl der Pins | 24 | — |
| Gehäuse | PDIP-24 | 24-pin PDIP (0.300 inch) |
| Betriebstemperatur | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Process Technology | CMOS EPROM | CMOS EPROM |
| Programmable Flip-Flops | 16 | — |
| Input Pins | 24 | — |
| Output Pins | 16 | — |
| I/O Compatibility | TTL | — |
| Program/Erase Method | UV (windowed) or OTP | — |
| RoHS-Status | Non-compliant (legacy PDIP) | Not applicable (legacy non-compliant package per distributor listing) |
| Device Family | — | Classic EPLD (EP610) |
| Macrocells | — | 16 |
| Maximum Pipeline Frequency | — | 33.3 MHz (typical) / 100 MHz pipelined |
| Montageart | — | Through-Hole |
| Programmability | — | One-Time Programmable (OTP, no window on plastic PDIP) |
| Output Drive Current | — | [DATA_NEEDED: IOH/IOL per datasheet DC characteristics] |
| Input Pins (Dedicated) | — | [DATA_NEEDED: dedicated input count from datasheet pinout] |
| I/O Pins | — | [DATA_NEEDED: bidirectional I/O count from datasheet pinout] |
| Programming Tool | — | Altera A+PLUS / MAX+PLUS II (legacy) |
| Lead Free Status | — | Not applicable |
| Current Distributor | — | Rochester Electronics, LLC (authorized continuing source) |