EP610PI-25 vs EP610DC-25 Vergleich
Detaillierter Direktvergleich von EP610PI-25 von Rochester Electronics und EP610DC-25 von Rochester Electronics. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Rochester Electronics
EP610PI-25 - 16-Macrocell Classic EPLD, 25ns DIP-24 | Rochester
EP610PI-25 ObsoleteRochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ AktivSpezifikationsvergleich
| Parameter | EP610PI-25 | EP610DC-25 |
|---|---|---|
| Marke | Rochester Electronics | Rochester Electronics |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $20,50 | $9,95 |
| Product Type | Erasable Programmable Logic Device (EPLD) | EPLD (Erasable Programmable Logic Device) |
| Series | Classic EP610 | — |
| Macrocells | 16 | 16 |
| Usable Gates | ~300 gates | — |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Internal Frequency (fCNT) | [DATA_NEEDED: fCNT] | — |
| Number of Dedicated Inputs | 4 | 4 |
| Number of Bidirectional I/O Pins | 16 | — |
| Gehäuse | 24-pin DIP (PI) ceramic through-hole | 24-pin CDIP (Ceramic DIP, through-hole) |
| Betriebstemperaturbereich | Industrial (I suffix): -40C to +85C | — |
| Supply Voltage (VCC) | 5 V nominal | 4.75 V to 5.25 V (5 V nominal) |
| Process Technology | CMOS, UV-erasable | — |
| Programmable Flip-Flop Modes | D, T, JK, SR (per macrocell) | — |
| Global Clock Pins | 1 | — |
| Montageart | Through-Hole (DIP) | Through Hole |
| Lead-Free / RoHS | [DATA_NEEDED: RoHS] | — |
| Original Manufacturer | Altera (now Intel PSG; legacy stock from Rochester Electronics) | — |
| Family | — | Altera Classic EPLD |
| Equivalent Gates | — | 300 |
| Maximum Propagation Delay (tPD) | — | 25 ns |
| Pipelined Data Rate | — | Up to 100 MHz |
| Number of I/O Pins | — | 22 |
| Total Pin Count | — | 24 |
| Betriebstemperatur | — | 0 C to +70 C |
| Technology | — | CMOS EPROM (UV-erasable) |
| Programming Method | — | JEDEC fuse-map / UV-erase |
| Speed Grade Suffix | — | -25 (25 ns tPD) |