EP910DI-30 vs EP9100C-30 Vergleich

Detaillierter Direktvergleich von EP910DI-30 von Rochester Electronics und EP9100C-30 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910DI-30 EP9100C-30
Marke Rochester Electronics Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $17,60 $7,95
Product Type UV-Erasable Programmable Logic Device (EPLD) —
Family Classic EPLD (Altera EP910 series) Altera Classic EPLD
Macrocell Count 24 —
Propagation Delay (tpd) 30 ns —
Maximum Toggle Frequency (fmax) 62 MHz —
Supply Voltage (VCC) 5 V (single supply) 4.75 V to 5.25 V (5 V nominal)
Technology CMOS, UV-erasable EPROM CMOS, UV-erasable (window) or OTP
Gehäuse CDIP-40 (ceramic DIP, 40-pin with UV window) 40-pin ceramic DIP (CDIP) / 44-pin PLCC (windowed) / 40-pin PDIP
Montageart Through-Hole (DIP) Through-Hole (DIP) / Surface Mount (PLCC)
Dedicated Inputs 10 24
Dedicated I/O Pins 12 (12 input + 12 output) —
Output Enable Pins 2 —
Pin-Anzahl 40 —
Programmable Logic Element JEDEC fuse map (3rd-party programmer) —
Betriebstemperatur -40C to +85C (industrial) 0C to +70C (commercial)
RoHS-Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: rohs_status]
Manufacturer (Original) Altera (now Intel PSG) —
Current Distributor / Authorized Aftermarket Rochester Electronics, LLC —
Logic Density — 900 usable gates (approx.)
Macrocells — 48
Flip-Flops — 24
Propagation Delay (tPD) — 30 ns
Maximum Toggle Frequency (fMAX) — 62.5 MHz
I/O Standard — TTL-compatible
Programming Method — JEDEC via Altera APU or compatible programmer
Military Grade Variant — EP9100C-30/883 (MIL-STD-883 compliant)

Datenblätter & Ressourcen

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