EP910IDC-15 vs EP910DC-35 Vergleich

Detaillierter Direktvergleich von EP910IDC-15 von Altera und EP910DC-35 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910IDC-15 EP910DC-35
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $9,95 $10,95
Manufacturer Altera (now Intel PSG) —
Family Classic EPLD Classic EPLD EP910
Equivalent Gates 450 —
Macrocells 24 24
Flip-Flops 48 —
Pin-to-Pin Delay (tPD) 15 ns —
Maximum Frequency (fCNT) 66.6 MHz —
Supply Voltage (VCC) 5 V —
Gehäuse 40-pin CDIP (Ceramic DIP, through-hole) 40-pin CDIP (Ceramic DIP) with quartz window
Terminal Count 40 —
Terminal Form Through-Hole —
Temperature Grade Commercial (0C to +70C) —
Programmable Security Bit Yes —
On-board Test Circuitry Yes —
Logic Type UV Erasable EPROM-based —
I/O Pins 24 24
Dedicated Inputs 10 12
Programming Technology EPROM (UV-erasable) —
RoHS-Status non_compliant (ceramic DIP contains lead) Non-compliant (ceramic DIP with Pb-bearing lead finish)
Device Type — UV-Erasable CMOS PLD (PAL-type)
Architecture — PAL-type sum-of-products AND-OR array
Usable Gates — 900 gates
Product Terms — 240
Total Inputs — 36
Propagation Delay (tpd) — 35 ns
Maximale Taktfrequenz — 37 MHz (typical, internal)
Supply Voltage (Vcc) — 4.75 V to 5.25 V (5 V nominal)
Betriebstemperatur — 0 °C to +70 °C (commercial)
Lead Pitch — 2.540 mm
Termination Style — Through-Hole
Programming Method — JEDEC fuse map via device programmer; UV erase
Technology — CMOS, UV-erasable EPROM cell
Lifecycle — Obsolete / last-time-buy from authorized distributors

Datenblätter & Ressourcen

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