EP910IDC-15 vs EP910DI-35 Vergleich

Detaillierter Direktvergleich von EP910IDC-15 von Altera und EP910DI-35 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910IDC-15 EP910DI-35
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Aktiv
Lagerstatus In Stock In Stock
Stückpreis (USD) $9,95 $35,20
Manufacturer Altera (now Intel PSG) Original Altera; long-term authorized by Rochester Electronics, LLC
Family Classic EPLD Altera Classic EPLD
Equivalent Gates 450 —
Macrocells 24 24
Flip-Flops 48 —
Pin-to-Pin Delay (tPD) 15 ns —
Maximum Frequency (fCNT) 66.6 MHz —
Supply Voltage (VCC) 5 V 4.75 V to 5.25 V (5 V nominal)
Gehäuse 40-pin CDIP (Ceramic DIP, through-hole) CDIP-40 (Ceramic DIP with UV window)
Terminal Count 40 —
Terminal Form Through-Hole —
Temperature Grade Commercial (0C to +70C) —
Programmable Security Bit Yes —
On-board Test Circuitry Yes —
Logic Type UV Erasable EPROM-based —
I/O Pins 24 —
Dedicated Inputs 10 10
Programming Technology EPROM (UV-erasable) —
RoHS-Status non_compliant (ceramic DIP contains lead) [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified]
Product Type — EPLD (Erasable Programmable Logic Device)
Usable Gates — 450
Propagation Delay (tPD) — 35 ns
Maximum Toggle Frequency (fCNT) — 28.6 MHz
Supply Current (ICC) — 40 mA typical
Bidirectional I/O Pins — 20
Total Pins — 40
Montageart — Through-Hole
Betriebstemperatur — -40C to +85C (industrial)
Technology — CMOS, UV-erasable EPROM
Programming Method — EPROM programmer + JEDEC fuse map
Erasure Method — UV light through quartz window
Logic Family — PAL-type AND/OR array with D flip-flops

Datenblätter & Ressourcen

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