EP910ILC-25 vs EP910ILC-12 Vergleich
Detaillierter Direktvergleich von EP910ILC-25 von Intel und EP910ILC-12 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910ILC-25 | EP910ILC-12 |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,95 | $12,40 |
| Family | EP910 Classic EPLD | Altera EP910 Classic EPLD |
| Macrocells | 24 | — |
| User I/O Pins | 36 | — |
| Propagation Delay (tPD) | 25 ns | 12 ns (max) |
| Internal Frequency (fMAX) | [DATA_NEEDED: fMAX rating] | — |
| Logic Blocks | Sum-of-products AND/OR array | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| Configuration Memory | Non-volatile EPROM (windowed ceramic) | — |
| Gehäuse | 44-pin JLCC (windowed ceramic) | 28-PLCC (J-Lead, 11.5 x 11.5 mm) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | -40C to +85C (industrial) | -40 °C to +85 °C (industrial grade, 'I' suffix) |
| Versorgungsspannung | 5 V | — |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| RoHS-Status | non_compliant (ceramic windowed package) | [DATA_NEEDED: RoHS status] |
| Lebenszyklusstatus | Obsolete - last time buy was late 1990s | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Number of Macrocells | — | 24 |
| Usable Gates | — | 450 (typical) |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Nominal Supply | — | 5 V |
| Memory Technology | — | UV-erasable CMOS EPROM |
| Configuration Storage | — | Non-volatile EPROM (instant-on) |
| Programming Method | — | Altera programming algorithm (serial/parallel master-slave) |
| MSL-Level | — | [DATA_NEEDED: MSL level] |
| Anzahl der Pins | — | 28 |
| Feedback Paths | — | 16 dedicated |