EP910IPC-15 vs EP910IPC-50 Vergleich
Detaillierter Direktvergleich von EP910IPC-15 von Altera und EP910IPC-50 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910IPC-15 | EP910IPC-50 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,95 | $13,85 |
| Device Family | Altera Classic EPLD (EP910 series) | — |
| Product Type | Erasable Programmable Logic Device (EPLD) | Erasable Programmable Logic Device (EPLD) |
| Architecture | PAL-type, CMOS | — |
| Macrocells | 24 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Product Terms | 240 | — |
| External Clocks | 2 | — |
| Propagation Delay (tPD) | 15 ns | 50 ns |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (5 V nominal) |
| Betriebstemperatur | 0C to +70C (commercial, IPC suffix) | -40C to +85C (industrial) |
| Gehäuse | PDIP-40 (Plastic DIP, 40-pin) | 40-pin Ceramic DIP (IPC, windowed) |
| Montageart | Through-Hole | Through-Hole (DIP) |
| Process Technology | CMOS | — |
| Programming Method | JEDEC fuse map via Altera EPLD programmer | Off-board EPROM programmer + UV erase |
| Pin-Anzahl | 40 | — |
| RoHS-Status | [DATA_NEEDED: rohs status not confirmed in verified data] | [DATA_NEEDED: not stated in verified data] |
| Family | — | Altera Classic EPLD |
| Logic Capacity | — | [DATA_NEEDED: macrocell count / equivalent gates] |
| Clock-to-Output (tCO) | — | 35 ns |
| Maximum Toggle Frequency | — | [DATA_NEEDED: fMAX] |
| User I/O Pins | — | 24 |
| Technology | — | CMOS EPROM cell |
| Erasure Method | — | UV light through ceramic window (IPC package) |