EP910JC-35 vs EP910DC-40 Vergleich
Detaillierter Direktvergleich von EP910JC-35 von Altera und EP910DC-40 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910JC-35 | EP910DC-40 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,95 | $13,95 |
| Logic Family | Classic EPLD (CMOS EPROM) | — |
| Macrocells | 24 | 24 |
| Inputs | 36 | — |
| I/O Pins | 24 | — |
| Propagation Delay (max) | 38 ns (tPD) | — |
| Maximale Taktfrequenz | 28.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Betriebstemperatur | 0C to 70C (Commercial) | — |
| Package Type | 44-pin PLCC (Plastic J-Lead Chip Carrier) | — |
| Montageart | Surface Mount (PLCC socket recommended) | Through-Hole |
| Terminal Form | J BEND | — |
| Package Code | QCCJ | — |
| Package Shape | SQUARE | — |
| Technology | CMOS EPROM, UV-erasable / OTP | — |
| RoHS-Status | [DATA_NEEDED: rohs status] | [DATA_NEEDED: rohs_status] |
| Temperature Grading | COMMERCIAL | — |
| Equivalent Gates | Approx. 900 usable gates | — |
| Device Family | — | Classic EPLD (EP910 series) |
| Architecture | — | PAL-type AND/OR, UV-erasable CMOS |
| Dedicated Inputs | — | 12 |
| Bidirectional I/O Pins | — | 24 |
| Total Inputs to Logic Array | — | 36 |
| Product Terms | — | 240 maximum |
| Maximum Propagation Delay (tPD) | — | 40 ns |
| Maximum Operating Frequency (fMAX) | — | 25 MHz |
| Global Clocks | — | 2 |
| Versorgungsspannung | — | 5 V (typical for Classic EPLD family) |
| Operating Temperature (Commercial) | — | 0 °C to 70 °C |
| Gehäuse | — | DIP-40 (ceramic, through-hole) |
| Programming Method | — | UV-erase + EPROM programmer; on-board logic test circuitry |